Since the invention of the integrated circuit, the semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization continues, the further shrinking of the process node may increase the complexity of fabricating integrated circuits and corresponding testing methods.
As semiconductor technologies evolve, wafer testing methods have become more sophisticated. In the semiconductor process, integrated circuits are fabricated on a semiconductor wafer. The semiconductor wafer goes through many processing steps before a plurality of integrated circuits are separated by cutting the semiconductor wafer. Each step of the semiconductor fabrication process may employ a variety of semiconductor tests and measurements to ensure consistent high quality. The variety of semiconductor tests and measurements include measuring carrier mobility and resistivity.
A Hall-Effect measurement is employed to measure the carrier mobility of a wafer. More particularly, when a Hall-Effect measurement is applied to a region of a wafer, a series of voltage measurements are performed with a constant current applied to the region of the wafer. In addition, a constant magnetic field is oriented in a perpendicular position relative to the region of the wafer. The Hall-Effect measurement may further include a second set of voltage measurements by reversing the direction of the magnetic field. In other words, a first set of voltage measurements may be obtained through a positive magnetic field. Likewise, a second set of voltage measurements may be obtained through a negative magnetic field. By employing both a positive magnetic field and a negative magnetic field, a more accurate carrier mobility testing result may be obtained.
The van der Pauw technique is used to determine the resistivity of a region of a wafer. The region may be of a rectangular shape, square shape or the like. The region comprises four corners numbered from 1 to 4 in a counter clockwise order. A dc current is injected between a first corner and a second corner. A voltage is measured across a third corner and a fourth corner. As such, a resistance of the specific region can be determined by using Ohm's law.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.